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CAT24C164
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
Ratings
–65 to +150
–0.5 to +6.5
Units
° C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than ? 0.5 V or higher than V CC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than ? 1.5 V or overshoot to no more than V CC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
N END (Note 3)
T DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program/Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC ? Q100
and JEDEC test methods.
3. Page Mode, V CC = 5 V, 25 ° C.
Table 3. D.C. O PERATING CHARACTERISTICS ( V C C = 1.8 V to 5.5 V, T A = ? 40 ° C to +85 ° C, unless otherwise speci ? ed.)
Symbol
Parameter
Test Conditions
Min
Max
Units
I CCR
I CCW
I SB
I L
V IL
V IH
V OL1
V OL2
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Read, f SCL = 400 kHz
Write, f SCL = 400 kHz
All I/O Pins at GND or V CC
Pin at GND or V CC
V CC ≥ 2.5 V, I OL = 3.0 mA
V CC < 2.5 V, I OL = 1.0 mA
? 0.5
V CC x 0.7
1
1
1
1
V CC x 0.3
V CC + 0.5
0.4
0.2
mA
mA
m A
m A
V
V
V
V
Table 4. PIN IMPEDANCE CHARACTERISTICS (V CC = 1.8 V to 5.5 V, T A = ? 40 ° C to +85 ° C, unless otherwise speci ? ed.)
Symbol
C IN (Note 4)
C IN (Note 4)
I WP (Note 5)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
Conditions
V IN = 0 V
V IN = 0 V
V IN < V IH , V CC = 5.5 V
Max
8
6
200
Units
pF
pF
m A
V IN < V IH , V CC = 3.3 V
V IN < V IH , V CC = 1.8 V
V IN > V IH
150
100
1
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC ? Q100
and JEDEC test methods.
5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull ? down is relatively strong;
therefore the external driver must be able to supply the pull ? down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V CC ), the strong pull ? down reverts to a weak current source.
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